Copyright 2009 Structured Design Verification Ltd.
Leveraging Formal Protocol definitions
The TransactorWizard toolset leverages Formal protocol descriptions to generate ready-to-use transactors.
  • Write once, get many approach for the lowest overall cost
  • Generates Master/initiator, slave/responder & monitor transactors from the same source
  • Easy to re-configure transactors by changing bus widths, transaction ordering models, etc.

TransactorWizard checks protocol for ambiguity before generation to improve quality and reduce debug

TransactorWizard generates transactors for many views from a common source
  • SystemC / SCV cycle-accurate models
  • Verilog / VHDL co-simulation
  • SystemVerilog co-simulation
  • Verilog co-emulation

Universal Transaction-Level Interface (UTLI) supports connection to virtually any transaction-level interface and provides consistent interfacing between co-simulation and co-emulation
  • additional support for OSCI TLM 2.0 b_transport() and nb_transport() interfaces

TransactorWizard automatically adds waveform, coverage & transaction-recording features as required
  • SCV, CSV-text and proprietry transaction recording
  • instrumentation for protocol-specific functional coverage

The available tools and ready-to-use IP....